This invention relates in general to techniques for simulating logic devices and generating test programs for testing those devices from data resulting from such simulations and in particular, to a technique for compressing simulations of logic devices to reduce the run time and data storage requirements for those simulations, and subsequently decompressing data resulting from those simulations and generating test programs for testing the logic devices from the decompressed data.
FIG. 1 illustrates an example of a logic device 10 having a plurality of inputs 20 and a plurality of outputs 30. Although there are no restrictions on the number or arrangement of the inputs or outputs to the logic device 10, for descriptive purposes the plurality of inputs 20 is shown in the figure to include four inputs 201-204 entering on one side of the logic device 10 and the plurality of outputs 30 is shown to include three outputs 301-303 exiting on the opposite side of the logic device 10.
The logic device 10 comprises digital circuitry which responds to electrical signals received through the plurality of inputs 20 by processing those signals at a speed determined by a supplied clock signal (not shown), and generating electrical signals in response thereof which are then transmitted through the plurality of outputs 30. The maximum speed at which the digital circuitry can operate is generally determined by the process technology used in fabricating the device.
FIG. 2 illustrates an example of a test configuration for testing the logic device 10. The logic device 10 is tested by a logic device tester 50 having a plurality of test channels 60. Some of the test channels 60 are connected to the plurality of inputs 20 of the logic device 10 to provide stimuli to the logic device 10, and some of the plurality of test channels 60 are connected to the plurality of outputs 30 of the logic device 10 to receive the responses of the logic device 10 to the provided stimuli.
A test program being executed on the logic device tester 50 is provided with a sequence of test vectors particular to the logic device 10 for testing the logic device 10. Each test vector includes a set of input values (also referred to herein as an "Input Vector") which are simultaneously applied across the inputs 20 of the logic device 10, and a set of expected output values (also referred to herein as an "Output Vector") which are expected to be simultaneously detected across the outputs 30 of the logic device 10 in response to the set of input values.
When testing the logic device 10, the logic device tester 50 sequentially applies each input vector across the inputs 20 of the logic device 10, detects each set of output values across the outputs 30 of the logic device 10 in response to each input vector applied, and compares the detected set of output values against the expected output values corresponding to the input vector being applied at that time by the logic device tester 50. When a detected output value on any one of the outputs 30 does not match its corresponding expected output value, the logic device tester 50 determines that the logic device 10 has failed. The speed at which the logic device tester 50 sequentially applies each of the input vectors across the inputs 20 of the logic device 10 is typically selected to be less than the maximum clock frequency of the logic device 10.
FIG. 3 illustrates an example of sequential input vectors being applied to the inputs 20 of the logic device 10. In a first input vector corresponding to time t0, signal 201' indicates that a HIGH logic level ("1") voltage is being applied to the input 201, signal 202' indicates that a LOW logic level ("0") voltage is being applied to the input 202, signal 203' indicates that a HIGH logic level voltage is being applied to the input 203, and signal 204' indicates that a HIGH logic level voltage is being applied to the input 204. Other input vectors corresponding to times t1 through t8 are also shown.
FIG. 4 illustrates an example of output values being detected on outputs 30 of the logic device 10 by the logic device tester 50 in response to the applied input vectors of FIG. 3. In a first set of detected output values corresponding to the input vector being applied at time t0, signal 301' indicates that a LOW logic level voltage is being detected on output 301, signal 302' indicates that a HIGH logic level voltage is being detected on output 302, and signal 303' indicates that a LOW logic level voltage is being detected on output 303. Other sets of detected output values corresponding to the input vectors being applied at times t1 through t8 are also shown.
In order to determine whether the logic device 10 has failed or not, the logic device tester 50 needs to compare each detected output value with a corresponding expected output value for that output in response to the input vector being applied at that time. FIG. 5 schematically illustrates how the expected output values are obtained. Simulated versions (e.g., 201"-204") of the input signals (e.g., 201'-204' in FIG. 3) are provided to a computer program 10" which simulates the logic device 10. The computer generated outputs (e.g., 302"-303") are then tabulated and corresponding values of the simulated inputs (e.g., 201"-204") are combined with their computer generated outputs (e.g., 301"-303") to form a test vector for each of the simulated time periods (e.g., t0, t1, t2, etc.).
FIG. 6 illustrates, as an example, a tabulation of test vectors (also referred to herein as "simulation data") for the first nine simulated time periods (e.g., t0 through t8) of the computer simulation described in reference to FIGS. 3-5. For the first nine simulated time periods, it is assumed for descriptive purposes that the expected output values, 301"-303", are equal to the actual detected output values, 301'-303'.